1. Field of the Invention
The present invention relates to a pillar-type field effect transistor having low leakage current, and more particularly, to a pillar-type field effect transistor capable of reducing gate induced drain leakage by forming a semiconductor body on a semiconductor substrate and forming a plurality of gate electrodes having different work functions so as to lower a work function of a gate electrode in a region overlapped with a drain region.
2. Description of the Related Art
DRAM technology has been one of the important technologies in silicon semiconductor markets. Recently, the DRAM technology has been more actively researched to implement next-generation highly-integrated DRAMs. In particular, a gate length of a DRAM cell device has been designed to be further reduced according to miniaturization of cell devices and an increase in a degree of integration of cell devices. As a problem in the miniaturization of cell devices, there is a so-called short channel effect problem. Due to the short channel effect, an off-state drain current is increased.
In a conventional MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), a channel region is formed in a planar surface, and source/drain regions are formed on both sides of the channel region. If the conventional MOSFET having the planar channel region is adapted to a sub-100 nm DRAM technology, the aforementioned short channel effect problem becomes serious. In general, in the miniaturization of the MOSFET, a thickness of a gate insulating layer and a depth of source/drain junction need be reduced, and a doping concentration of the channel region needs to be increased. In comparison with a Logic MOSFET, in the MOSFET for a DRAM cell device, the thickness of the gate insulating layer cannot be greatly reduced in terms of device characteristics, and the depth of the source/drain regions cannot be greatly deepened. Therefore, the miniaturization of the DRAM cell device is difficult. In addition, in order to prevent the so-called DIBL (Drain Induced Barrier Lowering) involved with the miniaturization of the DRAM cell device, the doping concentration of the channel region needs to be increased. In this case, a field between the channel region and the drain region is increased, and a leakage current due to band-to-band tunneling is increased. In the DRAM cell device, the leakage current, that is, an off-state drain current needs to be limited to about 1 fA or less. Therefore, in the conventional MOSFET having the planar channel, it is very difficult to reduce the gate length of the cell device down to about 70 nm or less.
Recently, approaches for solving the problems in the conventional DRAM cell device having the planar channel have actively researched. As an approach, a three-dimensional device structure or a device structure having a non-planar channel has been researched. As representative devices for the DRAM cell device, there are a device having a buried channel structure and a bulk FinFET, of which characteristics are described below.
In the DRAM cell device, it is important to decrease a cell area in a two-dimensional surface and to increase an on-state current and decrease an off-state current. In the buried channel structure, by preventing an increase in the cell area in the two-dimensional surface and increasing an effective channel length, the short channel effect such as DIBL can be suppressed. As an example, a buried channel structure adapted to a DRAM cell device was proposed by SAMSUNG ELECTRONIC CO. (J. Y. Kim et al., The breakthrough in data retention time of DRAM using recess-channel-array transistor (RCAT) for 88 nm feature size and beyond, in Proc. Symp. on VLSI Tech., p. 11, 2003). Although the off-state current can be greatly decreased by suppression of the short channel effect, the on-state current is also greatly decreased due to a relatively long channel length and a relatively short width of channel. Due to the decrease in the on-state current, operating speed of the DRAM is lowered. In addition, since a channel formed in the vicinity of a bottom of a buried region is formed in a concave shape, a problem of a back-bias effect become serious. In addition, any change in doping concentration of the channel region in the vicinity of the bottom causes a great change in a threshold voltage. In general, in the buried channel structure, the doping concentration is increased in only the buried channel region. In this case, the doping concentration influences the corner regions. In addition, in the ministration of device, a width of the buried channel region is reduced, so that it is difficult to control an etching profile in the vicinity of the bottom of the buried channel region and to maintain a uniform depth of the buried channel region. In addition, due to the reduction of the width of the buried channel region and the corresponding change in the etching profile in the vicinity of the bottom of the buried channel region, a sensitivity of the threshold voltage is increased.
In a double/triple-gate MOSFET where a gate surrounds a channel region, an excellent controllability of the gate electrode to the channel can be obtained. However, the double/triple-gate MOSFET formed on a SOI substrate, that is, an SOI FinFET cannot be substantially adapted to a DRAM cell device due to its device characteristics. The inventor of the present invention firstly proposed a body-tied double/triple-gate MOSFET (see Korean Patent Nos. 0458288 and 0471189, U.S. Pat. No. 6,885,055, Japanese Patent Application No. 2003-298051, U.S. patent application Ser. No. 10/358,981, and Japanese Patent Application No. 2002-381448), which is referred as a bulk fin field effect transistor (bulk FinFET). In the bulk FinFET, a channel is not buried, but the channel is formed in an upper surface and both side surfaces of a fence-shaped body. Alternatively, the channel is formed in both side surfaces of the fence-shaped body. As a result, the controllability of the gate electrode to the channel is much greater than that of the conventional device having the planar channel structure. In the bulk FinFET, the short channel effect can be effectively suppressed, and the DIBL becomes small, so that the miniaturization of device can be effectively implemented. Due to the excellent controllability of the gate electrode of the channel, there is substantially no influence of substrate bias. Since the cell area in two-dimensional surface is small and the effective channel width can be effectively increased, the on-state current can be increased, so that the operating speed of the DRAM can be increased. Therefore, a DRAM cell device employing the bulk FinFET can obtain many advantages.
In general, in an n-type FinFET, an n+ polysilicon gate is used. In this case, since the threshold voltage of a device is decreased, there is a problem in that the off-state current is increased. In order to increase the threshold voltage, a doping concentration for the channel region may be increased. However, the increase in the doping concentration causes an increase in the leakage current due to the band-to-band tunneling between the drain region and the channel region. There is a limitation in increasing the doping concentration for the channel region. In order to solve the problem, a negative word-line scheme may be used. However, there is a problem in that peripheral circuits become complicated. Alternatively, in order to increase the threshold voltage, the work function of the gate electrode may be changed by replacing the doping type of n+ with the doping type of p+. However, in this case, an energy band curvature in an overlapped portion between the gate electrode and the drain region is increased, so that the GIDL current is increased. As a result, there is a problem in that the off-state current is increased.
Therefore, the present invention proposes a new device structure capable of obtaining a suitable threshold voltage and a leakage current of 1 fA or less per cell by suppressing the GIDL in a pillar-type device.